A New Reseeding Technique for LFSR-Based Test Pattern Generation

In this paper we present a new reseeding technique for LFSR-based test pattern generation suitable for circuits with random-pattern resistant faults. Our technique eliminates the need of a ROM for storing the seeds since the LFSR jumps from a state to the required state (seed) by inverting the logic value of some of the bits of its next state. An eflcient algorithm for selecting reseeding points is also presented, which targets complete fault coverage and minimization of the cardinality of the test set and the hardware required f o r the implementation of the test pattern generator. The application of the proposed technique to ISCAS '85 and the combinational part of ISCAS '89 benchmark circuits shows its superiority against the already known reseeding techniques with respect to the length of the test sequence and, in the majority of cases, the hardware required for their implementation.